Satyavir Kumar Singh

About Satyavir Kumar Singh

An enthusiastic Physical Design Engineer with a B.Tech in Electronics and Communication from DTU and over 2 years of experience in SoC design and verification at NXP Semiconductors. Proficient in the RTL-to-GDSII flow, including synthesis, floorplanning, CTS, placement, routing, and timing closure. Skilled in Cadence and Synopsys tools, with a solid foundation in Verilog, VLSI and scripting. My past experiences include: • Physical Implementation of chip_top: Led Synthesis, Equivalence Checks, CLP, and PnR-related activities for an automotive SoC on 40nm technology, from specification to tape-out, optimizing QoR by 15%. • ECO Resolution: Implemented 50+ engineering change orders (ECOs) to fix functional bugs and timing issues. • Congestion Management: Successfully conducted 15 floorplan iterations and executed the critical flash-to-central buffering and routing of 1,900 nets at chip_top, significantly reducing congestion to under 1%. • Design Methodology Support: Developed the \'APR DASHBOARD\' automation for efficient Power, Performance, and Area (PPA) reporting across Cadence and Synopsys tools, improving debugging accuracy by 30%. Feel free to connect with me at s••••••••@gmail.com or call me at 85••••••22

Experience

1. Design Enablement Engineer (Physical Design)

   Renesas Electronics

   May 2025 — Present · Noida, IN

Education

• Delhi Technological University (Formerly DCE)

  Bachelor of Technology - BTech

  2019 — 2023

• DAV Public School Ara Bihar

  Matriculation

  2015 — 2016

• Gyanodaya Public School Delhi

  Intermediate

  2016 — 2018