Satyanarayana Hammigi
Timing Engineer @NVIDIA
Santa Clara, CA, US
EMAILS
s•••••••@nvidia.com
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Feb 2025 — Present
Timing Engineer @NVIDIA
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Santa Clara County, CA, US
EDUCATION
2002 — 2004
PSG College of Technology
ME ECE
1996 — 2001
University BDT College of Engg Davangere
BE
SKILLS
Logic SynthesisPhysical DesignSocArmAsicVerilogFormal VerificationSystem on a Chip (Soc)DftTclApplication-Specific Integrated Circuits (Asic)VlsiVery-Large-Scale Integration (Vlsi)Integrated Circuit DesignMicroprocessorsStatic Timing AnalysisVhdl
ABOUT SATYANARAYANA HAMMIGI
Experienced Senior Member Of Technical Staff with a demonstrated history of working in…
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