Satyabrata Sarangi

About Satyabrata Sarangi

My areas of interest include Micro-arch/RTL Design for FPGA/ASIC platforms, Low Power Digital IC Design, Formal Verification, Designing Accelerators on Many-core Processors, and VLSI Digital Signal Processing. Personal webpage - https://sites.google.com/site/satyabratavlsi/

Experience

1. Asic Design Engineer

   Meta

   Sep 2022 — Present · Sunnyvale, CA, US

   AI/ML (MTIA) and Video Transcoding (MSVP) ASICs Micro-architecture and RTL design C vs RTL datapath formal verification Logic optimization for synthesis/timing/PD closure

Education

• Indian Institute of Technology, Kharagpur

  Master's degree, Microelectronics and VLSI Design

• Biju Patnaik University of Technology, Odisha

  Bachelor of Technology (B.Tech), Electronics and Telecommunication Engineering

• University of California, Davis

  Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering: Major - VLSI Design and Computer Systems

Skills

• Big Data Analytics
• Fpga
• Irsim
• Multisim
• Static Timing Analysis
• Synopsys Tools
• Biomedical Electronics
• Magic Layout Design Software
• Arm7
• C++
• Hadoop
• Digital Signal Processing
• Digital Signal Processors
• Analog Circuit Design
• Biomedical Device Design
• Processors
• Logic Design
• Very-Large-Scale Integration (Vlsi)
• Signal Processing
• Simulink
• Xilinx Ise
• Electronics
• Algorithms
• Latex
• Nc-Verilog
• Vhdl
• Simulations
• Verilog
• Pspice
• Matlab
• Xilinx
• Modelsim
• Ni Multisim
• Mapreduce
• Vlsi
• Cadence Virtuoso
• Embedded Systems
• Code Composer Studio