Satya Pullela
Senior Engineering Management
- Role
- Sr Architect at Synopsys Inc
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Satya Pullela
EDA professional with broad experience in the areas of Emulation, Prototyping and FPGA / ASIC Static Timing Analysis, Statistical Timing, Circuit Simulation, Delay Calculation, Signal Integrity & Noise and Large Scale Software Systems development, CTS and Place & RouteSpecialties: Combinatorial and Numerical Algorithms, Optimization,VLSI Design, Statistics, Signal Processing, Programming, Distributed and Multi-core software development, and Computer Languages including C++, lex, & yacc.Several Scripting languages including Perl and Tcl/Tk.
Experience
Sr Architect
Jan 2024 — Present
Education
The University of Texas at Austin
Ph.D, Electrical and Computer Engg
Indian Institute of Science (IISc)
M.E, Electrical Engg
1989 — 1991
Indian Institute of Technology, Madras
B. Tech, Electrical Engg
1985 — 1989
Skills
- Perl
- Eda
- Vlsi
- Asic
- Very-Large-Scale Integration (Vlsi)
- Signal Processing
- Semiconductors
- Verilog
- C++
- Signal Integrity
- Application-Specific Integrated Circuits (Asic)
- Statistics
- Static Timing Analysis
- Communications Audits
- Lex
- Programming
- Algorithms
- Physical Design
- Timing
- Tcl
- Yacc
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