Satvik Goel
R&D Engineer (FPGA) || RTL Design || CXL
- Role
- R & d Enginner 1 at Qbit Labs Private Limited
- Location
- Gurugram, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
R & d Enginner 1
Jan 2024 — Present · Gurugram, IN
Education
Madan Mohan Malaviya University of Technology
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
2019 — 2023
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