Satvik Goel
R&D Engineer 2 (FPGA) || RTL Design || CXL
- Role
- R & d Engineer 2 at Qbit Labs Private Limited
- Location
- Delhi, DL, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Satvik Goel
I am an FPGA and RTL Design Engineer with experience in developing high-performance…
Experience
R & d Engineer 2
Apr 2025 — Present · Gurugram, IN
Education
Madan Mohan Malaviya University of Technology
Bachelor of Technology - BTech
2019 — 2023
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.