Satish Patil
Principal Design Engineer at Cadence Design Systems
- Role
- Principal Design Engineer at Cadence
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Satish Patil
Experienced Systems Engineer with interests in DSP and Embedded systems. Strong engineering professional with a Master of Technology (M.Tech.) focused in Electrical Engineering (specialization - Electronic Systems) from IIT Bombay.
Experience
Principal Design Engineer
Jul 2021 — Present · Pune, IN
Education
Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded
BTech, Electronics and Tele-communications Engineering
2008 — 2012
Indian Institute of Technology, Bombay
MTech, Electrical Engineering
2013 — 2016
Skills
- Windows
- Very-Large-Scale Integration (Vlsi)
- Spice
- Embedded C
- Matlab
- C
- Programming
- Algorithms
- Analog and Mixed Signal Vlsi Design
- Cadence Virtuoso
- Leadership
- Vlsi
- C++
- Mixed-Signal Ic Design
- Analog Circuit Design
- Image Processing
- Adcs
- Integrated Circuit Design
- Java
- Verilog
- Cmos
- Vhdl
- Ubuntu
- Linux
- Sigma-Delta Adcs
- Layout
- Latex
- Scilab
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.