Satish Kumar Gupta
Design Verification Methodology Engineer
- Role
- Soc Design Engineer at Intel
- Location
- Redmond, WA, US
- LinkedIn followers
- 500 followers
About Satish Kumar Gupta
Experienced Senior Automation Engineer with a demonstrated history of working in the semiconductors industry. Skilled in EDA, Layout Versus Schematic (LVS), Physical Design, Application-Specific Integrated Circuits (ASIC), and Debugging. Strong engineering professional with a Master of Technology - MTech focused in Micro electronics from Birla Institute of Technology and Science, Pilani.
Experience
Soc Design Engineer
Apr 2022 — Present · Hillsboro, OR, US
PESG-ITPM Team
Education
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Micro electronics
2015 — 2017
Bhilai Institute of Technology, Durg
Bachelor of Engineering (BE), Electronics and Telecom(ET&T)
2001 — 2005
Skills
- Layout Versus Schematic (Lvs)
- Debugging
- Virtuoso
- Silicon
- System on a Chip (Soc)
- Soc
- Design Rule Checking (Drc)
- Static Timing Analysis
- Simulations
- Application-Specific Integrated Circuits (Asic)
- Physical Verification
- Mixed Signal
- Physical Design
- Very-Large-Scale Integration (Vlsi)
- Perl
- Eda
- Cadence Virtuoso
- Vlsi
- Asic
- Drc
- Lvs
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