Satish Singh

About Satish Singh

Experience -* Microarchitecture specification and RTL design…

Experience

1. Senior Staff Engineer Manager

   Qualcomm

   Aug 2016 — Present · Bengaluru, IN

   Machine Learning accelerator for pre-processing Video/Images for NSP * Lead team of 4 RTL designers * Achieved significant improvement in NSP inference performance- Design of Application Process Subsystem for low power SoC * Integration of ARM M55 core and subsystem- Design of high throughput, low power Shared memory core *>10 MB of on-chip memory * OSPI XIP slave for external memory access- Design of ALU instructions for an inhouse DSP processor * Design of DSP processor using ASIP core tool from Synopsys using high-level nML- Design of Digital Tx and Rx inhouse 40G SerDes * Worked with Analog team to define the specs of Digital circuit requirements to test Analog SerDes- Design of full Testchip for SerDes * Full SoC containing two instances of SerDes- PCIE bridge connecting Cache coherent Fabric to PCIE Gen4 controller * Highly complex design at 1.2GHz for ARM server SoC

Education

• University of Colorado Boulder

  MS, Electrical Engineering, Major: Communication and Signal Processing.

  2002 — 2004

• Indian Institute of Technology, Guwahati

  B. Tech, Electronics and Communication Engineering

  1998 — 2002

Skills

• Systemverilog
• Hardware Architecture
• Vera
• Phy
• Verilog
• Soc
• Rtl Design
• Amba Ahb
• Functional Verification
• Open Verification Methodology
• Asic
• Modelsim
• Vhdl
• Microprocessors
• Fpga
• Ethernet
• Microarchitecture
• Vlsi
• Debugging
• Logic Design
• Processors
• C
• Arm
• Digital Signal Processors
• Embedded Systems
• Very-Large-Scale Integration (Vlsi)
• Field-Programmable Gate Arrays (Fpga)
• Application-Specific Integrated Circuits (Asic)
• System on a Chip (Soc)