Satish Sajjanar

About Satish Sajjanar

DFT Engineer specializing in ASIC and SoC design with strong focus on DFT architecture, ATPG, silicon debug, and test methodology development• Hands-on across the complete DFT lifecycle: early architecture planning, RTL-level testability checks, gate-level bring-up, ATPG execution, coverage analysis, and production test enablement• Extensive experience working on large, highly hierarchical SoCs with multi-million scan flops, multiple partitions, and complex test modes• Strong expertise in scan-based DFT, including stuck-at, transition, and low-power ATPG, along with TME implementation and entry verification (RTL & GLS)• Proven capability in silicon debug and root-cause analysis, including tester correlation, failure analysis, and resolution of test escapes• Hands-on exposure to DC parametric, leakage, IDDQ, burn-in, boundary scan, LBIST test flows• Experienced in debugging and integrating complex third-party IPs such as memory subsystems and high-speed interfaces• Strong interest in DFT automation and methodology development, leveraging Tcl, Perl, and Python to improve efficiency, scalability, and test quality• Contributor to technical papers, tutorials, and internal knowledge-sharing initiatives in the DFT and test domain• Collaborative team player with a passion for mentoring engineers, cross-functional coordination, and driving best DFT practices• Motivated by solving challenging silicon problems and delivering robust, high-quality, first-pass test patterns

Experience

1. Asic Design for Testability Engineer, Silicon

   Google

   Jan 2026 — Present · Bengaluru, IN

Education

• K H Kabbur Institute of Engineering

  Diploma, Electronics and Communication Engineering

  2011 — 2014

• New English School

  10th

  2010 — 2011

• PES University

  Bachelor of Engineering, Electronics and Communication Engineering

  2014 — 2017