Satish Gupta
Principal Design Engineer at Cadence
- Role
- Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Satish Gupta
Design Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in SV, UVM, JESD, ORAN, PCIe RTL Debugging, and C (Programming Language). TB development and maintenance. Coverage activities. Exposure to GLS, formal verification. Strong engineering professional with a Master of Technology (M.Tech.) focused in Advanced communication systems from National Institute of Technology Warangal.
Experience
Principal Design Engineer
May 2025 — Present · Bengaluru, IN
Education
National Institute of Technology Warangal
Master of Technology (M.Tech.), Advanced communication systems
2013 — 2015
ABES Engineering College
B.tech, Electronics and Communication Engineering
2008 — 2012
Skills
- Firmware Automation
- Express Pcb
- Embedded Systems
- C
- Matlab
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.