Satya Marni

About Satya Marni

Qualified technical personality with 24+ years of physical design experience in SemiCon Industry and a prior 4+ years with Academia. A proven track record of successfully taped-out complex SoC devices at the leading edge process technology nodes.A self starter, fully focused and having consistent track record in delivering commitments under tight schedules. In-depth understanding of all design aspects, EDA, Manufacturing, IP and Semiconductor products.Specialties: • Technical Management, Motivator and Executive Leadership• Established Physical Design teams from scratch at various geographies (India, Singapore & US)• Team competency development• Current team size ~300 spanning India (BLR,HYD), Cairo, Vietnam (Da Nang & HCMC) & USA• Low power design techniques and implementation• System On Chip design (180nm to 2nm)• Involved in more than 20 chips so far• Program Chair & Jury member at various prestigious conferences• Double MS in E&C and VLSI CAD from BITS, Pilani and MAHE, Manipal respectively

Experience

1. Sr Director R & d Physical Design

   新思科技股份有限公司

   Feb 2024 — Present · Karnataka, IN

Education

• Andhra University

  BE, ECE

  1993 — 1995

• Birla Institute of Technology and Science, Pilani

  MS, E & C

  1997 — 1999

• Manipal Academy of Higher Education

  MS, VLSI CAD

  2000 — 2001

Skills

• Fpga
• Asic
• Vlsi
• Integrated Circuits (Ic)
• Soc
• Floorplanning
• Tcl
• Technical Management
• Technology Management
• Eda
• Lvs
• Cadence
• Ic
• Primetime
• Semiconductor Design
• Timing Closure
• Clock Tree Synthesis
• Mixed Signal
• Rtl Design
• Physical Design
• Team Building
• Logic Synthesis
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Dft
• Low-Power Design
• Arm
• System on a Chip (Soc)
• Drc
• Very-Large-Scale Integration (Vlsi)
• Static Timing Analysis
• Semiconductors