Sathish Kumar Appusamy
R&D IC Design Engineer - DFT
- Role
- R & d Ic Design Engineer - Dft at Broadcom
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sathish Kumar Appusamy
Experience in multi-million gate SOC and mixed signal IPs- Good understanding of the Cadence, Mentor & Synopsys EDA based flows for DFT development- Key expertise in ATPG includes Stuck at, Transition, IDDQ & Path delay- Expertise in SOC ATPG setup creation- Handling Analog Mixed Signal IPs from ATPG perspective- Worked on gate level simulation for both Timing & NoTiming- Experience in verification of the 1149.1 JTAG BSCAN - Experience in post Silicon debugs (Shmoo Analysis, Vmin, Fmax, etc.)- Experience in Fault Analysis and debugs on customer returned devices- Involvement in multiple yield debugs. Worked very closely with Design/PD team to root cause the issues- Experience in working with cross-functional teams - STA/PD (locally) and Product engineering (globally) teams- Experience in MBIST insertion using Tessent Mentor Tool- Experience in STA constraint cleanup for DFT modes
Experience
R & d Ic Design Engineer - Dft
Jul 2017 — Present · Bengaluru, IN
Education
Sona College of Technology
B.E, Electronics & Communication Engineering
2005 — 2009
Amrita School of Engineering, Bangalore
M.Tech, VLSI Design
2009 — 2011
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