Sathish Kannappan
SEG@Apple
- Role
- Soc Physical Design Engineer at Apple
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Soc Physical Design Engineer
Jan 2024 — Present · Cupertino, CA, US
Education
PSG college of Technology
BE
1998 — 2003
Skills
- Tcl
- Soc
- Semiconductors
- Timing Closure
- Static Timing Analysis
- Very-Large-Scale Integration (Vlsi)
- Physical Design
- Circuit Design
- Verilog
- Perl
- Eda
- Application-Specific Integrated Circuits (Asic)
- Lvs
- Ic
- Vlsi
- Rtl Design
- Asic
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