Sathish Jajimoggala

About Sathish Jajimoggala

Have 5.8 years of experience and currently working with Google in Physical design with the main responsibilities of synthesis, static timing analysis, logic equivalence check, pnr and sign-off at block level and timing closure at full chip level. Good understanding PnR flow, timing constraints, clock tree synthesis, static timing analysis concepts, timing eco and exposure of DFT constraints/implementation.

Experience

1. Silicon Engineer

   Google

   Apr 2022 — Present · Bengaluru, IN

   Bengaluru, Karnataka, India

Education

• Narsimha Reddy Engineering College, Hyderabad

  Bachelor’s Degree

  2008 — 2012

• Indian Institute of Space Science and Technology

  Master’s Degree

  2014 — 2016

Skills

• Physical Design
• C
• Programming
• Field-Programmable Gate Arrays (Fpga)
• Cadence Virtuoso
• Matlab
• Rtl Verification
• Verilog Hdl
• Rtl Design
• C++
• Static Timing Analysis
• Cadence Virtuoso Layout Editor
• Vhdl
• Microsoft Office
• Logic Synthesis