Sathish Dadi
- Role
- Design Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Engineer
Jun 2014 — Present
Block level Netlist generation from RTL. Layout completion STA RF Design Low power techniques
Skills
- Debugging
- Perl
- Digital Designs
- Static Timing Analysis
- Verilog
- Rf Design
- Modelsim
- Computer Architecture
- Rtl Design
- Vlsi
- Circuit Design
- Primetime
- Asic
- Logic Synthesis
- Vhdl
- Fpga
- C
- Systemverilog
- Very-Large-Scale Integration (Vlsi)
- Floorplanning
- Microprocessors
- Integrated Circuit Design
- Icc
- Presto
- Dcc
- Clock Tree Synthesis
- Soc
- Xilinx
- C-Language
- Logic Design
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