Satheesh Balasubramanian

About Satheesh Balasubramanian

Current Role and Responsibilities:Member of the Advanced Product Group in the Physical IP Group at Arm. Key responsibilities include developing methodologies for Variability modelling, High Sigma Signoff, Low Voltage functional and timing signoff.Summary of current interests:Machine Learning (ML) Techniques for EDAData Analytics - identifying data patterns across datasetsExternal Contributions:Expert Reviewer - DAC and Tau ConferencesTrack Judge - EDA conferencesPanelist - Discussion on Low Voltage Design Challenges - Tau 2016Summary of Past Experience:Experience in all aspects of standard cell library development - library architecture analysis, circuit design, characterization, functional and timing validation, QAExtensive work on development of parametric measurement modules to enable silicon debug on high volume SoC\'sCollaborated extensively with Fab engineers and product managers to ensure high yield tapeouts and quick silicon bring upFab Experience:Hands on working experience in a class 10 Fab at the Pennsylvania state universityWorked on taking a raw wafer through all steps of manufacturing processes to fabricate and characterize test circuits on siliconWorked on analyzing the impact of hydrogenation on the behavior of nickel silicide as part of Master\'s thesis

Experience

1. Distinguished Engineer

   Arm

   Apr 2021 — Present · IN

Education

• P.S.Senior Secondary School

  High School

  1985 — 1996

• Indian Institute of Technology, Madras

  B.Tech, Metallurgical Engineering

  1997 — 2001

• Indian Institute of Technology, Madras

  Bachelor of Technology - BTech, Metallurgical Engineering

• Penn State University

  M.S., Solid state devices and circuits

  2001 — 2004

Skills

• Low-Power Design
• Semiconductors
• Eda
• Circuit Design
• Cadence Virtuoso