Sathappan Ravi
Principal Design Engineer, DDR PHY at Apple
- Role
- Principal Design Engineer, Ddr Phy at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sathappan Ravi
Specialties: DDR / LPDDR PHY design, DDR Architectures, High Speed Datapath, Logic Design, Memory Training Algorithms, Verilog, System Verilog, Python
Experience
Principal Design Engineer, Ddr Phy
Oct 2021 — Present · Cupertino, CA, US
Education
PSG College of Technology
B.E, Electronics and Communication Engineering
2005 — 2009
UCLA
Master of Science - MS, Electrical and Electronics Engineering
2010 — 2012
Skills
- Rtl Design
- Verilog
- Fpga
- Functional Verification
- Formal Verification
- Cadence Virtuoso
- Asic
- Matlab
- Integrated Circuit Design
- Systemverilog
- Vhdl
- Ic
- Phy
- Ddr
- Digital Design
- Digital Hardware Design
- Memory Controllers
- Digital Electronics
- Vlsi
- Xilinx
- Debugging
- C
- C++
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