Satendra Maurya

About Satendra Maurya

Professional R&D engineer with 9+ years’ experience in digital high-speed circuit design. Extensive experience in diverse elements of circuit design from full custom (L2/L3 dual-rail Cache memory and data path macro for mobile and server microprocessor), semi-custom macros (TLB and Cache for radiation hardened MIPS processor) to fully synthesizable designs (EPON/GPON framers). Indepth expertise in all physical implementation aspects of fully custom digital circuit design (IPCAM design) utilizing dynamic and static design techniques. Through understanding of various design aspects for timing characterization and energy optimization. Developed several in-house tools to achieve high frequency low power design targets. Experience in the full design cycle: Architecture, circuit design and optimization, circuit design methodology, physical implementation, automation, characterization, timing and model generation, and post-silicon validation. Strong communication skills and collaborative attitude. Ability to technically lead complex projects, while simultaneously owning and implementing complex circuit functions. Proven track record of 1st pass design success.

Experience

1. Sr Principal

   Ampere

   Sep 2018 — Present · Raleigh, NC, US

   Working on high performance custom cache memory for leading edge Ampere Servers processors

Education

• Arizona State University

  MS, VLSI

  2007 — 2009

• National Institute of Technology, Tiruchirappalli

  B Tech., Electronics and Communication Engineering

  2000 — 2004

• Arizona State University

  PhD, EE

  2009 — 2011

Skills

• Mixed Signal
• Asic
• Soc
• Rtl Design
• Fpga
• Architecture
• Microprocessors
• Embedded Systems
• Vlsi
• Vhdl
• Processors
• Computer Architecture
• Low-Power Design
• Verilog
• Circuit Design
• Testing
• C
• Electronics
• Application-Specific Integrated Circuits (Asic)
• Field-Programmable Gate Arrays (Fpga)