Saswat Padhy

About Saswat Padhy

Low Power Design Engineer with good understanding & experience in -ASIC low power design and implementation across mobile, compute,XR/AR/VR GPUs-Understanding of GPU & processor architecture[ARM/RISC-V] with AMBA protocols[AHB/AXI] & memory subsystems -Power characterization using PTPX/Power Artist for various GPU cores for different GPU benchmarks-Participate in defining power management schemes and low power modes like clock gating, power gating, DVFS, voltage islands etc-Explore power optimization opportunities in RTL with Power Artist/ RTL-A for enhanced PPA-Create power specifications,UPF definition & power intent validation using CLP-Experience in digital design of low-power IPs with Verilog-Perform power estimation, roll, up and tracking through all phases of the project using PTPX-Explore power optimization opportunities & suggest ways to improve power, and drive PPA convergence-Experience with ASIC low power aware synthesis, LEC/FM non-equivalence debugs-Participate in pre/post-silicon power co-relation & debugs-Understanding of timing critical paths analysis using Prime-time-scripting with tcl/python

Experience

1. Senior Silicon Design Engineer

   AMD

   Mar 2025 — Present · Bengaluru, IN

Education

• Khallikote (Autonomous) College, Berhampur

  INTERMEDIATE , SCIENCE

  2012 — 2014

• International Institute of Information Technology Bangalore

  Master of Technology - MTech, VLSI and circuit designing

  2019 — 2021

• International Institute of Information Technology Bangalore

  Mas, Electrical and Electronics Engineering

• Veer Surendra Sai University Of Technology (VSSUT,Formerly UCE), Burla

  Bachelor's degree, Electrical Engineering Technologies/Technicians

  2014 — 2018

• D.A.V. Public School - India

  MATRICULATION , SCIENCE

  2002 — 2012