Shashi Preetham
RTL & FPGA Design Engineer | Digital Logic | Verilog, VHDL, Vivado
- Role
- Design and Verification Trainee at Maven Silicon
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Shashi Preetham
FPGA Design Engineer with 2 years of experience in RTL design, verification, and digital…
Experience
Design and Verification Trainee
Jan 2022 — Present · Bengaluru, IN
Education
Vardhaman College of Engineering (VCEH)
Bachelor of Technology - BTech
2019 — 2023
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.