Sasi Kanth Chennupati

Aspiring ASIC Physical Design Engineer | ASIC Verification Engineer | Teaching Assistant for VLSI physical Design and Verification.

Role
Sr Application Engineer at Cadence
Location
Fresno, CA, US
LinkedIn followers
500 followers
Information TechnologyView LinkedIn profile

About Sasi Kanth Chennupati

I\'m Senior Masters student in Electrical and Computer Engineering at California State University, Fresno, with a focus on VLSI and experience in Verilog, System Verilog, UVM, and Cadence Virtuoso. I\'m looking for full-time opportunities beginning in March 2022. I was bought-up playing with the electronic circuits all around. I love Physics, so I was into the Electronics and Communication Engineering for the bachelor degree. That eventually, drew my interest on to semiconductors and Integrated Circuits. I keep trying to solve the real-world problems with these skills in hand, so that I face the different challenges. That helped me in gaining skills. I believe in hands-on experience, so I\'m habituated to deploy the topics I cover academically and check if it really works. This experience always helped me in critical developing my skills.My skills are as follows:• Verilog, system Verilog, UVM, • Embedded-C, Python• RTL Design Verification, Synthesis, Static Timing Analysis, ASIC Design flow• Simulation/EDA tools: Cadence Innovus, Cadence Virtuoso, Synopsys Design Complier, Xilinx Vivado, MATLAB.Projects:• Designing a “Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing”. • Designed a MAC unit and performed synthesis to obtain area, power and timing reports using Design Compiler. Our goal is to run placement, optimization, clock tree synthesis, and routing on our design to finally generate GDS file• Design of Hetro-junction TFET using TCAD.If you believe my profile meets your requirements, reach me at s••••••••@mail.fresnostate.edu or +15•••••••01.

Experience

  1. Sr Application Engineer

    Cadence

    Jul 2022 — Present · San Jose, CA, US

Education

  • California State University, Fresno

    Masters of Electrical and Computer Engineering, Electrical and Computer Engineering

  • SRM IST Chennai

    Bachelor of Technology in Electronics and Communication Engineering,, Electrical and Electronics Engineering

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Sasi Kanth Chennupati — Sr Application Engineer at Cadence in Fresno, CA, US | Unifers