Sashaank Kasturirangan

About Sashaank Kasturirangan

With over 11 years of experience as a Senior DFT Design Verification Engineer at Apple, I specialize in developing and maintaining verification test bench environments, creating directed and directed random tests, and enhancing test environments to address coverage gaps. My expertise includes Verilog, VLSI, and Cadence Virtuoso, which I leverage to verify complex designs and ensure robust hardware performance. At Apple, I contribute to the development of automated verification flows, functional coverage analysis, and design validation in collaboration with design leads and architects. I am committed to delivering high-quality results through innovative problem-solving and teamwork, with a focus on advancing cutting-edge hardware solutions.

Experience

1. Senior Dft Design Verification Engineer

   Apple

   Feb 2015 — Present

   Develop verification plans in coordination with design leads and architects.•Create and maintain verification test bench components and environments.•Generate directed and directed random tests.•Create automated verification flows for block verification.•Create functional coverage points, analyze coverage and enhance test environment to target coverage holes.•Apply knowledge of Hardware Description languages (VHDL, Verilog) and logic simulators to verify complex designs.

Education

• University of Texas at Dallas

  Master's Degree, Electrical and Electronics Engineering

  2012 — 2014

• SSN College of Engineering

  Bachelor of Engineering (B.E.), Electrical and Electronics Engineering

  2008 — 2012

Skills

• Perforce
• Debugging
• Cadence Design Suite
• Xilinx
• Systemverilog
• Cadence Virtuoso
• C
• Matlab
• Cadence
• C++
• Perl
• Tetramax
• Linux
• Modelsim
• Synopsys Verdi
• Tssi Tvt
• Microsoft Office
• Vlsi
• Verilog
• Simulations
• Perl Script
• Logic Design
• Unix
• Very-Large-Scale Integration (Vlsi)
• Mountaineering
• Xilinx Ise
• Electrical Engineering
• Digital Electronics
• Synopsys Tools