Sarveswara Tammali
- Role
- Senior Manager (R & d) at Broadcom
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
Research & DevelopmentView LinkedIn profile
About Sarveswara Tammali
Overall 20 years of industry experience in chip design. Profound knowledge in the area…
Experience
Senior Manager (R & d)
Aug 2018 — Present
Skills
- Soc
- Application-Specific Integrated Circuits (Asic)
- Asic
- Jtag
- Modelsim
- 1-Team Genesis
- Vlsi
- Verilog
- Logic Synthesis
- Testkompress
- Low Power Design
- Veritas Cluster Server
- Low-Power Design
- Joint Test Action Group (Jtag)
- Rtl Design
- Physical Design
- System on a Chip (Soc)
- Silicon Debug
- Pbist
- Spyglass
- Ncsim
- Dft
- Bist
- Eda
- Tetramax
- Low Power Test
- Atpg
- Fpga
- Very-Large-Scale Integration (Vlsi)
- Debugging
- Fastscan
- Integrated Circuit Design
- Mis
- Tessent Memorybist
- Vcs
- Automatic Test Pattern Generation (Atpg)
- Mbist
- Encounter Test
- Static Timing Analysis
- Ieee 1500
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