Sarthak Varshney
SoC Engineering Intern @Synopsys || Ex-Intern @LRDE DRDO || Ex-PRISM Intern @Samsung R&D Institute of India || Attended VIT VELLORE
- Role
- Soc Engineering Intern at 新思科技股份有限公司
- Location
- Gurugram, IN
- LinkedIn followers
- 500 followers
About Sarthak Varshney
I am working as an SoC Engineering Intern at Synopsys, specializing in Design Verification. I have developed testbench for the APB3 AMBA protocol using both SystemVerilog and UVM, written assertions for functional and formal verification, and gained hands-on experience with VCS, Verdi, HVP, and VC Formal. My expertise also covers verification methodologies, debugging, and formal verification flows. Alongside SoC design and verification, I have a strong background in antenna and microwave engineering. I designed a phased array antenna based on multilayer substrate integrated waveguide technology for beam scanning applications, which was published in at WPMC 2024 proceedings. I also hold a patent in antenna design, and I am currently working on wearable textile antennas for biomedical applications. During my B.Tech in Electronics and Communication Engineering, I graduated with a CGPA of 8.98 and topped my university in VLSI System Design. My academic journey was complemented by projects such as FPGA-based hardware systems and Astrobiology Head role in a rover prototype project that ranked in the top 20 globally at IRC’24.I bring a combination of technical depth, problem-solving ability, and research-driven mindset, with hands-on experience spanning SoC verification, HDL design, FPGA prototyping, and antenna R&D. I am eager to continue building my career in Semiconductor and system design, while also contributing to innovative research in RF and antenna domains.
Experience
Soc Engineering Intern
May 2025 — Present · Bengaluru, IN
Education
Delhi Public School, Sushant Lok
High School Diploma
2006 — 2021
Vellore Institute of Technology
Bachelor of Technology - BTech
2021 — 2025
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