Sarsij Saurabh
Formal Verification Engineer, India
- Role
- Asic Engineer, Formal Verification at Meta
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Experience
Asic Engineer, Formal Verification
Sep 2025 — Present · Bengaluru, IN
Education
Manipal Institute of Technology
Bachelor's Degree, Electronics and Communication Engineering
2008 — 2012
Nanyang Technological University
Master's Degree, Integrated Circuit Design
2014 — 2016
Technical University of Munich
Master's Degree, Integrated Circuit Design
2014 — 2016
Nanyang Technological University Singapore
Master of Science - MS, IC Design
Skills
- Formal Verification
- Verilog
- System Verilog
- C
- C++
- Rtl Design
- Soc
- Integrated Circuit Design
- Embedded Systems
- Vhdl
- Matlab
- Embedded Software
- Autosar
- Algorithms
- Vlsi
- Microcontrollers
- Debugging
- Programming
- Systemverilog
- Linux
- Electronics
- Asic
- System on a Chip (Soc)
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