Saritha Akkapalli
VLSI Design Verification Engineer at Capgemini Engineering
- Role
- Associate Ii Design Verification Engineer at Capgemini Engineering
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Saritha Akkapalli
3+ years of experience in VLSI ASIC Domain including SOC Verification and SubSystem level…
Experience
Associate Ii Design Verification Engineer
Feb 2024 — Present · Hyderabad, IN
Education
Valmiki Vidyalayam
9.8 CGPA
Trinity Junior College
Inter
2014 — 2016
Jawaharlal Nehru Technological University
Bachelor of Engineering - BE
2016 — 2020
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