Sarith Gopinathan
Layout Design Engineer @ Intel | Standard Cell & Custom Layout
- Role
- Layout Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Layout Design Engineer
May 2007 — Present
Education
State Board of Technical Education and Training
High School Diploma, Electrical, Electronics and Communications Engineering
NTTF (Nettur Technical Training Foundation)
Post Diploma in Power Electronics, Power Electronics
2001 — 2002
All India Council for Technical Education (AICTE)
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
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