Sarilla Sunanda
Physical Design Engineer @Capgemini Engineering
- Role
- Physical Design Engineer at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sarilla Sunanda
Passionate about semiconductor industry which led me to learn different skills needed to explore the semiconductor industry. I am seeking for a position in VLSI back-end domain in semiconductor industry to learn and showcase my skills and contribute to the growth. Possess capability of working with a team and alone.∎HDL: Verilog ∎EDA Tools • Prime Time • Fusion Compiler • Design Compiler • ICC2 • Tanner Tools • Mentor Graphics • Xilinx ISE∎Domain: ASIC Back-end Design and Verification ∎Operating systems • Linux • windows ∎Core SkillsRTL Coding using Synthesizable constructs of Verilog, FSM based design, Simulation, CMOS Fundamentals, Static Timing Analysis, Logic Synthesis, Floor planning, Placement, Routing, Signoff (ERC, DRC and LVS)∎Projects •Design of Two Stage Op-Amp Using CMOS Technology •RISC-V Processor using DC & ICC2∎Mini Projects: •Router 1×3 Using Fusion Compiler •Router 1×3 Design Using Verilog •Water Level Indicator •Heartbeat Sensor •Computer Gesture Controlling Using Arduino ∎Internship: Internship on VLSI from Apsis Solutions ∎Behavioral Skills •Communication •Organized
Experience
Physical Design Engineer
Nov 2024 — Present · Bengaluru, IN
Education
Maven Silicon VLSI Training Centre
Training , VLSI Physical Design
JNTU-GV
B.Tech, ECE
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