Hema Sai Sarath Kumar Jaladi
DFT Engineer @ INTEL || M.TECH (EI&ES)@NIT WARANGAL || EX FPGA RTL design engineer @ Medha Servo Drives
- Role
- Dft Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Hema Sai Sarath Kumar Jaladi
2 years of experience at RTL design, logic synthesis, implementation and FPGA prototyping…
Experience
Dft Engineer
Jun 2025 — Present · Karnataka, IN
Education
GMR Institute of Technology (GMRIT), GMR Nagar, Rajam, Srikakulam Dt.,-532127 (CC-34))
Bachelor of Technology - BTech, Electronics and Communications Engineering
2017 — 2021
National Institute of Technology Warangal
Master of Technology - MTech
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