Sarath Goriparthi

About Sarath Goriparthi

12+ years of experience as Analog Layout Engineer. Hands on experience with different processes like TSMC 7nnm, Samsung 10nm, ST 28FDSOI, ST 40 and 65nm, SAMSUNG 28nm, SONY 40nm, TSMC and Dongbu 180nm, BCD 350 and 500nm, TI 600nm.Successfully lead the team of 4 members for couple of projects.Trained custom layout aspirants on Analog layout design at Institute of Silicon Systems, HyderabadSound knowledge on fixing complex and challenging DRC in TSMC 7nm. Worked on IP or macro top level placement, routing and verification.Worked on complex and high-speed designs such as PLL(8GHz), CLK modules, ADC, DACAnd other high-speed blocks inside TX, RX for SERDES.Worked on high power designs such as Buck, Boost Regulators which has devices operating at different voltages 1.8V to 40V) and max current consumption up to 1A.Worked on power management circuits such as High Precision Bandgaps, High current LDO’s (up to 40mA) and BIAS circuits which generates bias currents for whole chip or IP.Ability to understand schematics and take care of critical things in layout.Good debugging skills on verification tools like Calibre, PVS, Assura, Star RC.Experience on working with designers to pass post-layout simulations.Experience on fixing EM and IR issues and generating LEF and DEF for digital teams.In-depth knowledge on matching, bias and clock signal routing, power planning, floor-planning, Shielding, Antenna, Latch-up.Good knowledge on DRC, LVS, SRD, DFM, PERC and LFD checks.

Experience

1. Senior Mask Layout Engineer

   NVIDIA

   Oct 2019 — Present · Santa Clara, CA, US

Education

• San José State University

  Master of Science - MS, Electrical Engineering

• AANM & VVRSR POLYTECHNIC, GUDLAVALLERU

  Diploma, Electrical, Electronics and Communications Engineering

  2008 — 2011

• IETE

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2011 — 2015