Sarath Chandra Nunna
SOC DESIGN ENGINEER INTEL
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Soc Design Engineer
Apr 2021 — Present · Bangalore Urban, IN
Working on SUBFC Design Planning which includes pin placement at both subfc & partition level.Feedthrough creation.Make FEV clean and deliver the collaterals to partition owners.Full chip Integration with health checks clean at SOC level.
Education
K L UNIVERSITY
Bachelor of Technology (B.Tech.)
2010 — 2014
K L UNIVERSITY
Bachelor of Technology (BTech)
2010 — 2014
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.