Saraswathi S
Aspiring VLSI Engineer | B.Tech in Electronics and Telecommunication | Honours in Embedded Systems | Digital Design & Verification
- Role
- Research Intern at Csir-Ceeri
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
About Saraswathi S
VLSI engineer skilled in RTL design and verification with practical command over Cadence Xcelium, NC-Wave for digital circuits, and Virtuoso for mixed-signal analysis. I have completed industry-grade projects at XChip Technologies, Bangalore (Zstandard compression pipeline) and Iravan Technologies, Pune (SPI protocol verification), and I am also experienced in Verilog/SystemVerilog, FSM-based design, and UVM concepts, with additional work in FPGA prototyping.
Experience
Research Intern
Dec 2025 — Present
Education
Sit Symbiosis Institute of Technology
Bachelor of Technology, Electronics and Communications Engineering
2022 — 2026
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