Saranya Vasudevan
Component Debug Engineer at Intel Corporation
- Role
- Component Debug Engineer at Intel
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Saranya Vasudevan
MSEE graduate from San Jose State University.My technical skills are as follows:Programming/ RTL Coding Skills: Verilog, System Verilog, PythonSkills: RTL Design, Digital Logic Design, Computer Architecture basics, Simulation, Synthesis, Static Timing Analysis, ASIC design flow, UVM, SCAN, BIST, Cover groups, AssertionsBus Protocols: AMBA APB, AHB, I2C, UARTEDA Tools: Synopsys VCS, Intel Quartus, Design Compiler, GTK wavesSoftware/ Software Tools: HP ALM, JIRA, Oracle DB
Experience
Component Debug Engineer
May 2021 — Present
Education
Anna University Chennai
Bachelor of Engineering (B.E.), Electrical and Electronics Engineering
2010 — 2014
San José State University
Master's degree, Electrical and Electronics Engineering
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