Saranya Devi Ganesan

About Saranya Devi Ganesan

Experienced and Passionate GPU Validation and Debug engineer with 7 years experience in Display Post Silicon Validation.• Leading the overall Display Power Management Features: Content development, Validation, Debugs and Test Plan Readiness. • Projects worked: Gen9, Gen11, Gen 11.5, Gen 12, Gen 13, Gen 14, Gen 15, Gen 16 • Expertise in resolving various Critical Customer Debugs pertaining to Display PM/Display/SOC. • Expertise in Display Feature enabling, debugging issues, leading V-teams which involves working with different stakeholders like architects, design engineers, presilicon, software teams, etc. to root cause, and to identify workarounds and solutions for critical failures. • Technically skilled on Intelx86 Architecture with expertise on Display IP hardware • Display Power Management feature expertise: Panel Self Refresh (PSR1, PSR2), Variable Refresh Rate (VRR), Frame Buffer Compression (FBC), Panel Replay (PR), ALPM, LRR, Port Sync and other intel specific PM features. • Expertise in latest eDP1.5 Industry Standard: Panel Replay, Auxless ALPM, Adaptive Sync AS SDP, CMRR • Display Protocol Knowledge: eDP 1.4/1.5, Display Port (DP), HDMI, MIPI • Good knowledge on Memory architecture and caching concepts and hands on with memory related debugs.•Display Identification Protocol: EDID, DID 2.0 • Silicon and board bring up during early Power-On Phase of new Intel silicons.*Validation Frameworks*• Experienced in Display BareMetal Validation Framework - C based driver independent framework. • Experienced in Python Debug Scripts • Worked on Perspec System Verifier -Cadence tool kit for validation. • Worked on Simics - Presilicon simulation environment. • Exposure to Pre-silicon Emulation environment • Fluent in SW development tools: debuggers, code revision systems: GitHub, Gitlab, etc.*Debug Tools*• Experience and hands on skills with JTAG interfaces like Lauterbach (LTB), ITP, • Hardware Debug Tools: VISA (Visualization of Internal Signals Architecture), Scan dumps and traceability Tools • Software Debug tools: Visual studio, WinDbg, Event Trace Log (eTL) • Logic Analyzers, Oscilloscopes, I2C captures, and in-circuit Emulators.

Experience

1. Graphics Hardware Engineer

   Intel

   Jun 2018 — Present · Bengaluru, IN

Education

• Sri Ramakrishna Engineering College

  Bachelor of Engineering - BE

• PSG College of Technology

  Master's degree

  2016 — 2018