Saran Kumar Seethapathi

About Saran Kumar Seethapathi

ASIC semi-custom Implementation from Netlist to GDSII with hands on experience in Synthesis, DFT, Floorplanning, Physical Design, Physical Verification, Formal Verification, IR/EM Analysis and Timing/Power analysis.Specialties: High performance Physical Design; Mulit-supply & Multi-voltage Physical Design (with UPF); Full chip timing closure; CTS / Clock Mesh design

Experience

1. Master Engineer

   Broadcom

   Jul 2011 — Present · Irvine, CA, US

Education

• College of Engineering, Guindy

  BE, Electronics and Communication

  2001 — 2005

Skills

• Digital Signal Processors
• Soc
• Rtl Design
• Semiconductors
• Arm
• Electronics
• Arm Architecture
• Ic
• Static Timing Analysis
• Dft
• Timing Closure
• Rtl Coding
• Vlsi
• Eda
• Asic
• Integrated Circuit Design
• Microprocessors
• Physical Design
• Verilog
• Tcl
• Processors
• Cmos
• Integrated Circuits (Ic)
• Primetime
• Rtl
• Application-Specific Integrated Circuits (Asic)
• Formal Verification
• Logic Synthesis