Sarang Nadkarni
- Role
- Design Verification Engineer at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Jul 2014 — Present
Skills
- Asic
- Manufacturing
- Synopsys Design Compiler
- Synopsys Tools
- Magic Layout Tool
- Tetramax
- Xilinx Ise
- Static Timing Analysis
- Digital Circuit Design
- Fpga
- Vlsi
- Assembly
- Hspice
- Integrated Circuit Design
- Cosmoscope
- Irsim
- Vhdl
- Verilog
- Computer Architecture
- Bsd Compiler
- C++
- Modelsim
- Tcl
- Rambist
- Spice
- Perl
- Synopsys Primetime
- C
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