Sarang Kalra
Senior Design Verification Engineer at Silicon Labs
- Role
- Senior Design Verification Engineer at Silicon Labs
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Senior Design Verification Engineer
Mar 2024 — Present · Hyderabad, IN
Education
Indian Institute of Technology, Bombay
M.Sc, Physics
2016 — 2018
Indian Institute of Technology, Bombay
Master of Technology - MTech, Solid State Devices (Microelectronics and VLSI)
2019 — 2021
Raman Research Institute
Research scholar, Theoretical Physics
2018 — 2019
Sri Venkateswara College, Delhi University
Bachelor's degree, Physics
2013 — 2016
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