Sunny K
Sr.Silicon Design Engineer at AMD | Power Estimation || PD
- Role
- Sr Silicon Design Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sunny K
5+ years Semiconductor Professional with relevant experience3+ years as Power Optimization and EMIR Engineer2 years as Physical Design(PnR) & STA- Currently working Power Estimation & EMIR at Xilinx-AMD- Expertise in PTPX Power analysis- Expertise in RTL Architect tool for fast synthesis - Expertise in PPRTL and PA Power analysis- Doing vector mapping debug using Verdi- A complete Place and Route Physical Design flow using Cadence-Innovus, Synopsys IC-Compiler- Worked for blocks with million gates count and 1.6GHz freq- Hands on experience on industry leader EDA tools - Working experience of a wider range of technologies (6nm, 7nm, 22nm, 28nm, 40nm, 65nm)- Organizational skills like Soft skills, Team player, Working experience in global teams across different time zones.Tools Having Hands on Experience:> Complete PnR - Innovus, ICC2> Power - PTPX and Verdi> ENIR - RedHawk_SC> fsdb analysis - Verdi> Timing Signoff - PrimeTime & Tempus> RC Extraction - STAR-RCXT- Worked on complete ASIC flow from Place and route to timing fixes and DRC/LVS cleanup.
Experience
Sr Silicon Design Engineer
May 2025 — Present · Hyderabad, IN
Doing ADIC based Power Estimation and Optimizations and Power Modeling
Education
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID
B.tech, ECE
2016 — 2020
Z.P.Hign School, Lakshmipuram, Visakhapatnam
SSC
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID
Pre University Course, PUC
2014 — 2016
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.