Santosh Kumar Krishnan
Senior Principal Design Engineer at Cadence Design Systems
- Role
- Senior Principal Design Engineer at Cadence
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
About Santosh Kumar Krishnan
6+ years of experience doing performance modelling and performance debugging for DDR controllers. Experienced with DDR4, DDR5, LPDDR4, LPDDR5/5x, LPDDR6 standards, and ARM AXI4 and CHI standards. I am currently working with SystemC, C++, TLM2, python, Verilog and System Verilog. I am currently responsible for Cadence DDR controller model correlation/accuracy and performance forecasting for new controller features.
Experience
Senior Principal Design Engineer
Jul 2025 — Present · Pune, IN
Education
UC San Diego
Master of Science (M.S.), Computer Engineering
2014 — 2016
Pune Institute of Computer Technology
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering
2010 — 2014
Skills
- C++
- Quartus Ii
- Matlab
- Tcl Programming
- Cadence Virtuoso
- Modelsim
- Synopsys Design Compiler
- Unix
- Ncverilog
- Fpga
- Data Structures
- Asic
- Xilinx Ise
- C
- Microsoft Office
- Vlsi
- Vhdl
- Synopsys Primetime
- Hspice
- Integrated Circuit Design
- Verilog
- Cadence Encounter
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