Santhosh V
Analog/Memory Layout Design Engineer at Capgemini Engineering
- Role
- Analog Layout Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Santhosh V
Expert in Memory Compilers/ Analog Layout/ Full custom layout
Experience
Analog Layout Design Engineer
Oct 2020 — Present
Education
Visvesvaraya Technological University
Bachelor of Engineering (B.E.), Electronics & Communication Engineering
2009
Skills
- Physical Verification
- Memory
- Verilog
- Physical Design
- Digital Electronics
- Particle Physics
- Quantum Mechanics
- Analog Circuit Design
- Semiconductor Fabrication
- Microelectronics
- Tcl
- Ic Layout
- Perl
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