Sannith Gadhepally
Design Verification Engineer | UVM | System Verilog | AXI4 | Functional Coverage & Assertions
- Role
- Design Verification Engineer at Soctronics
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sannith Gadhepally
Passionate about functional verification with hands-on experience in UVM, AXI protocols, and assertion-based design. I enjoy building testbenches, writing constraints, and diving deep into debugging. Always learning, always improving.
Experience
Design Verification Engineer
Aug 2023 — Present · Hyderabad, IN
Education
MLR Institute of Technology
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
2019 — 2023
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