Sanket Rahane
Silicon Engineer @ Google | Ex- Qualcomm | Physical Design, Timing
- Role
- Physical Design Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Physical Design Engineer
Jun 2024 — Present · Bengaluru, IN
Education
College of Engineering Pune
Master of Technology (MTech)
2015 — 2017
Skills
- Scan Compression
- Joint Test Action Group (Jtag)
- Verilog
- Scan Insertion
- Vhdl
- C++
- Tcl
- System Verilog
- Matlab
- Basic Html
- Embedded C
- C
- Java Script
- Automatic Test Pattern Generation (Atpg)
- Perl
- Design for Testability(Dft)
- Embedded Systems
- Mbist
- Rtos
- Physical Design
- Linux
- Bscan
- Synthesis
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