Sanket Phapale

About Sanket Phapale

Working at Samsung, having 7+ years of industrial experience in RTL design. I have completed M.tech in VLSI Design at VIT, Vellore. Seeking for an opportunity in front end design/RTL Design/Micro Architecture Design to enhance my analytical and technical skills. I have worked on following tasks.1. RTL Design/Microarchitecture2. Debug Support for Verification Team 3. Timing Fixes and Support to Back End Team 5. Quality Checks for RTL ( Lint, CDC etc) Technical Skill Sets:EDA Tools: Synopsis VCS,VerdiHardware Description Languages: Verilog, System Verilog.Scripting Languages: PerlOther: Static Timing Analysis, CDC, Low PowerArea of Interest: RTL Design and Micro-Architecture DesignDigital DesignASIC DesignStatic Timing AnalysisContact Details:1. Current LinkedIn Profile.2. Email: s••••••••@gmail.com

Experience

1. Staff Gpu Rtl Design Engineer

   Qualcomm

   Dec 2024 — Present · Bengaluru, IN

Skills

• Verilog
• Synopsys Tools
• Perl
• Tcl-Tk
• Application-Specific Integrated Circuits (Asic)
• Cadence Virtuoso
• Physical Design
• Static Timing Analysis
• Modelsim
• Altera Quartus
• Vhdl
• Xilinx Ise
• Matlab
• Embedded Linux
• Red Hat Linux
• Keil
• Ni Multisim
• Proteus
• Windows
• Electronics
• Linux
• Project Management
• Very-Large-Scale Integration (Vlsi)
• Leadership
• Management
• Integration
• Process Improvement
• Field-Programmable Gate Arrays (Fpga)
• Tcl
• Rtl Design
• Embedded C
• Eda
• Cmos
• Logic Synthesis
• Dft