Sankalp Jain

About Sankalp Jain

I have 12+ years of experience in Custom Layouts ranging from High Frequency Analog (RF Layouts) to High Precision Analog Layouts, Memory and IO layouts in Finfet, FDSOI & Planar (CMOS) across various technology nodes such as 5nm, 6nm, 7nm, 16nm, 22nm, 28nm, 65nm, 180nm, 500nm from different foundries like TSMC, GF, TI, Intel for multiple clients onsite in Bangalore, Bhubaneswar & Ottawa (Canada).1. Analog & Mixed signal layout -7 years : High frequency blocks - PLL, VCOs (operating at 16GHz, 12GHz,9GHz,6GHz) along with the its inductor design,ADC,Clock dividers,multiplexers,comparators,CML drivers,High speed - low power Clock buffers, Opamps including top modules handling high speed clocks ranging from 2.4GHz-16GHz. Worked on AIB 2.0 PHY used as chiplet interconnect operating at 6.4 Gbps.2. Memory Layouts - 8 Months : Worked on LIO (Local Input Output), LCTRL (Local Control), GCTRL ( Global Control) including Cap balancing for Sense amplifiers for better performance. IO layouts - 7 Months : Worked on development of LVCMOS library with 24 cells including Signal cells for 1.8V-3.3V, Thermal diode, Auxiliary Cells for 0.8V - 3.3V, Spacers. ESD : Worked on layout of 3.3V snapback clamp supporting CDM 9A.Along with these, worked on testcases development to check different requirements to meet ESD and latchup DRCs and guidelines for High, Moderate, Low and Ultra low Injectors.Custom layout responsibilities : Floorplan, Placement, Routing, Verification (DRC, LVS, DFM), Reliability Checks & fix for EM-IR, Antenna, Latchup, Density Fills, Parasitic extractions & layout optimization, PERC checks (LDL,CD,P2P,TOPO) for IO layouts, Exhaustive abutment checks to clean DRCs of various IO combinations from different libs.Exposure to layouts at bump and substrate level : Worked on Daisy Chain creation for a project to test robustness of Bumps. Got exposure to Allegro & Substrate Routing scenarios.Brief exposure for ~9 months to ASIC flow -RTL (designed ALU for 8 bit microprocessor)-Synthesis STA (Synthesized RTC IP using RTL compiler) clearing all setup / hold violations-Physical design using encounter for same synthesized IPs along with post layout STA timing closure.Tools exposure - Cadence Virtuoso (L, XL, EXL) for layout- Calibre, PVS, Pegasus, Assura verification for DRC, LVS, DFM - Calibre, Cadence QRC for parasitics- Voltus-Fi, Totem for EMIR- Calibre PERC Along with these, have basic knowledge of SKILL to automate basic layout tasks.

Experience

1. Senior Technical Lead - Mixed Signal Layout

   HCLTech

   Jul 2020 — Present · Bengaluru, IN

   Lead team (for layouts) with size ranging from 2-5 layout engineers for customer project in Analog layout and IO layouts domain.Opamp, ADC clock oscillator, Integrator, Averager : Worked on layout floorplan, routing, verification, reliability checks (EMIR, Antenna), density, post layout optimizations. Handled the top level & involved in guiding junior layout engineers and reviewing their work to ensure quality.Tech Node : GF22FDX (FDSOI 22nm)IO layouts : Worked & lead team on completion of LVCMOS library involving 24 cells ranging from signal cells operating at 1.8V, Open drain signal pad operating at 3.3V to Auxiliary cells operating at 1V, 1.8V and 3.3V, Thermal diode & Spacer cells. Involved in developments of testcases for various ESD, latch up rules for high, moderate and low noise injectors.Completed & fixed PERC ( LDL, P2P, CD) for all cells present in library.Exhaustive abutment DRC cleanup of IOs within same library and IOs from different libraries (LVDS).3.3V Snapback Clamp : Worked on layout and completion of 3.3V Snapback clamp supporting CDM 9A.Tech node : TSMC N6 (finfet 6nm)

Education

• MEDICAPS INSTITUTE OF TECHNO MANAGEMENT, INDORE

  Bachelor's degree

  2009 — 2013

Skills

• Drc
• Mixed Signal Physical Design
• Verilog
• Vhdl
• Static Timing Analysis
• Vlsi
• Analytical Skills
• Modelsim
• Lvs
• Cadence Virtuoso
• Physical Design
• Cadence Qrc
• Pvs Verifications
• Cmos
• Standard Cell Layouts
• Analog Layouts
• Asic
• Cadence Encounter