Sanjith Vishnu

About Sanjith Vishnu

As an experienced SoC Physical Design Engineer with a Master\'s in Electrical Engineering, I specialize in driving end-to-end RTL-to-GDSII physical design for cutting-edge semiconductor technologies, including 5nm and 3nm nodes. My expertise is in handling complex multi-voltage IP blocks, low-power design techniques, and sign-off flows, ensuring that each design meets stringent PPA targets.At Intel, I’ve played a key role in delivering innovative low-power solutions, automating and optimizing methodologies to boost project efficiency and performance. The strong foundation in VLSI, combined with my expertise in scripting and debugging enables me to take a hands-on, problem-solving approach.I\'m curious and a fast learner always looking forward to learning new tools and technologies. Apart from being an engineer, I am a photographer, avid skier, amateur boxer and guitarist, and a fitness enthusiast. Feel free to strike up a conversation about anything.

Experience

1. Soc Design Engineer (G6) - Physical Design

   Intel

   Feb 2026 — Present · Santa Clara, CA, US

   Promoted to Senior Engineer.IP - Structural Design- Owned physical implementation of complex CXL partitions (~2.5m instance count) from floor planning through final signoff- Drove timing closure across multiple corners and modes under aggressive PPA targets for high-frequency (~2GHz) clock domains- Built strong experience in congestion analysis within an IR-drop-sensitive partition, resolving routing hotspots while maintaining power and timing integrity- Gained expertise in section/tile level timing closure.

Education

• University of Cincinnati - College of Engineering and Applied Science

  Master of Science - MS, Electrical and Electronics Engineering

  2019 — 2021

• Kumaraguru College of Technology

  Bachelor of Engineering, Mechatronics

  2015 — 2019