Sanjeev Kumar Tyagi
PPAC Optimization | Advanced node DTCO | Reliability & Thermal Stability Analysis
- Role
- Hardware Engineer at Intel
- Location
- Beaverton, OR, US
- LinkedIn followers
- 500 followers
About Sanjeev Kumar Tyagi
As a seasoned semiconductor professional, I have extensive experience in power, performance, area, and cost (PPAC) analysis and optimization. While evaluating leading edge nodes for the same i also ensure the reliability and thermal stability using flows like Redhawk SC IR Drop analysis,Redhawk SC Self-heat/EM analysis & Fusion Compiler Regional thermal analysisI excel in power estimation, reduction, and profiling at block level. My proficiency in evaluating and optimizing performance metrics, analyzing and optimizing design area, and conducting cost-benefit analysis ensures efficient resource utilization and budget management in semiconductor projects.I am adept at designing RTL, conducting logic equivalence checks up-to signoff, performing SYNTHESIS, APR, STA for complex blocks. My background also includes FPGA validationI am passionate about leveraging my skills to contribute to cutting-edge projects and collaborate with cross-functional teams to achieve shared goals. Let’s connect and explore how we can work together to drive innovation and success in the semiconductor industry.
Experience
Hardware Engineer
Jan 2018 — Present · Hillsboro, OR, US
Education
Visvesvaraya Technological University
BE, Telecommunications
1999 — 2003
Skills
- Hardware Architecture
- Soc
- Vhdl
- Architectures
- Modelsim
- Architecture
- Clearcase
- Pcie
- C
- Integrated Circuit Design
- Microprocessors
- Vlsi
- Ip
- Static Timing Analysis
- Arm
- Rtl Design
- Field-Programmable Gate Arrays (Fpga)
- Internet Protocol (Ip)
- Systemverilog
- Debugging
- Verilog
- Application-Specific Integrated Circuits (Asic)
- Fpga
- Asic
- Tcl
- Eda
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