Sanjay Kumar Sardana

About Sanjay Kumar Sardana

PMIC Development: FUSA - UV, OV Voltage Monitors, Telemetry - ADC, AFE, PGA, Pin Detection, IO, Housekeeping- LDO, BGR, POR, OSC.Key Responsibilities:1). Development of VCM Buffer for SAR ADC2). Development of 5V to 42V and 42V to 5V Level Shifters3). Verification of Housekeeping Blocks such as LDO, BGR, OSC and POR4). Development of Under Voltage and Over Voltage monitors for FUSA Sub-System of Automotive PMIC-Specifications to Silicon.5). Telemetry-12 bit Split SAR ADC-Pin Detection feature-Programmable gain amplifier -Analog Front End-RTL development with digital team5). Analog Design Engineer: worked on RCD chip team (for DDR5)-Have experience in designing Tx, ZQCAL (calibiration algorithm) for High speed Interfaces-Good knowledge of Analog Mixed signal (AMS) simulations.6). Test & Product Engineering: Worked on test program development on ATE platform for production testing.7). Master Thesis work: Design of Noise Shaping SAR ADC and Nyquist Rate SAR ADC.8). Projects under coursework in post-graduation: Design of Analog Blocks such as Comparator, Amplifiers, Operational Amplifier, Sample & Hold Circuit, Precision Amplifier.Design of D Flip Flop, Asynchronous Set/Reset Flip Flop and Latches.Design of Current Steering DAC.Mathematical modelling of Analog to Digital Converters (Nyquist and Oversampled both): SAR ADC, Pipelined ADC, Delta Sigma ADC, MASH & SMASH ADC.Calibration & Dithering in Pipelined ADC.9). Internship Project: Design of VCO and Charge Pump based Phase Locked Loop.Experienced in MATLAB, Virtuoso, Calibre, SimVision, Altium, Allegro, LTSpice, Eagle Test Platform for ATE

Experience

1. Senior Analog Design Engineer

   Renesas Electronics

   Jan 2025 — Present

   PMIC Development: FUSA - UV, OV Voltage Monitors, Telemetry - ADC, AFE, PGA, Pin Detection, IO, Housekeeping- LDO, BGR, POR, OSC.Key Responsibilities:1). Development of VCM Buffer for SAR ADC2). Development of 5V to 42V and 42V to 5V Level Shifters3). Verification of Housekeeping Blocks such as LDO, BGR, OSC and POR4). Development of Under Voltage and Over Voltage monitors for FUSA Sub-System of Automotive PMIC-Specifications to Silicon.5). Telemetry-12 bit Split SAR ADC-Pin Detection feature-Programmable gain amplifier -Analog Front End-RTL development with digital team

Education

• Indian Institute of Technology, Kharagpur

  Master's degree, Microelectronics & VLSI

  2018 — 2020