Sanjay Churiwala

About Sanjay Churiwala

I have held multiple roles spanning front-end RTL for large wireless chips to EDA Tools (requirements gathering, development, applications, and testing).With technical expertise in STA, clock domain crossing/synchronization, power, synthesis, simulation, rule-based static checkers, cell characterization and modeling, and Xilinx design tools, I also possess expert debug skills, displaying a structured, problem solving approach.The recipient of several international patents, I have also written multiple technical books, published by Springer, New York and Europe. In addition, I have published many articles and papers in trade journals, conferences, and popular newspapers in multiple countries. I have also written numerous entries for the Xilinx Adaptable Advantage Blog. Having spent most of my career within a matrix-management structure, I am accustomed to cross-geographical as well as cross-cultural communication, to maintain the interest of multiple stakeholders. I also have deep relationships with several reputable engineering colleges in India.

Experience

1. Corporate Vice President

   AMD

   Feb 2022 — Present · Hyderabad, IN

Education

• Indian Institute of Technology, Kharagpur

  B Tech., Electronics

  1989 — 1993

Skills

• Semiconductors
• Logic Synthesis
• Debugging
• Rtl Design
• Fpga
• Asic
• Static Timing Analysis
• Vlsi
• Simulations
• Hardware
• Soc
• Verilog
• Ic
• Embedded Systems
• Eda
• C