Sanitha V Sadasivan

VLSI Layout Engineer @ Intel | Test Chip Layout | M.Tech VLSI (VIT) | Trained in Physical Design | DRC | Cadence

Role
Layout Engineer at Intel
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Sanitha V Sadasivan

VLSI Layout Engineer at Intel with over 3 years of hands-on experience in Test Chip Layout across advanced semiconductor technology nodes. I currently work on full-custom layout development, contributing to silicon validation and technology bring-up through precise and efficient layout implementation.I have had the opportunity to work on multiple Intel technology nodes, including 7nm, 5nm, 10nm, 14nm, 16nm, and Intel 18A, where I have independently owned layout design activities and handled complete physical verification, including resolving all DRC issues prior to sign-off.I hold an M.Tech in VLSI Design from VIT, Vellore, and have been formally trained in Physical Design, giving me a solid foundation in both custom and digital layout methodologies. My skill set includes floorplanning, test chip layout design, routing, DRC verification, and proficiency with top-tier EDA tools like Cadence Virtuoso and Mentor Calibre.

Experience

  1. Layout Engineer

    Intel

    Mar 2022 — Present · IN

    VLSI Layout Engineer at Intel with 3+ years of hands-on experience in Test Chip Layout for advanced semiconductor technology nodes. Currently working on full-custom layout development, focusing on enabling silicon validation and technology bring-up through precise and efficient layout implementation.I hold an M.Tech in VLSI Design from VIT, Vellore, and have been formally trained in Physical Design, giving me a strong foundation in both custom and digital layout methodologies. My skill set spans across test chip layout, DRC verification, and working with top-tier EDA tools such as Cadence VirtuosoCollaborative, detail-oriented, and always keen to explore emerging technologies in the semiconductor space. I thrive in cross-functional environments and enjoy contributing to first-silicon success and design quality.

Education

  • Technical Higher Secondary School Puthuppally

    Higher Secondary Education, Electronic and Electrical

    2005 — 2010

  • College of Engineering ,Kidangoor

    Bachelor of Technology - BTech, Electronics and Communication

    2010 — 2014

  • Vellore Institute of Technology

    Master of Technology - MTech, VLSI Design

    2016 — 2018

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Sanitha V Sadasivan — Layout Engineer at Intel in Bengaluru, KA, IN | Unifers